The present invention relates to the packaging of integrated circuits (ICs) and more particularly to an array quad flat no-lead (QFN) package and a method of forming the array QFN package.
A conventional QFN package typically comprises an IC die attached and electrically connected to a lead frame. The IC die, the electrical connections and a portion of the lead frame are encapsulated by a mold compound, leaving a portion of the leads exposed. The exposed leads serve as input and output (IO) connections to the encapsulated IC die and are typically located along a periphery of the QFN package. Because QFN packages provide a number of advantages over other lead frame package configurations including, for example, shorter electrical paths and faster signal communication rates, QFN packages are widely used as low pin count solutions for power elements. A drawback, however, is that the number of I/O connections on such packages is limited. Increasing the number of I/O connections on a QFN package necessitates reducing lead pitches or spacing between adjacent leads. Unfortunately, the reduction of lead pitches increases the likelihood of cross-talk and signal interference, and complicates the manufacturing process. Thus, a need exists for an array QFN package and a simple and inexpensive method of forming such a package.